The optimal placement of forced-convection cooled microchips of different power-consumption rates is investigated for minimizing the microchip temperatures. The analytical solution based on the constant-property assumption agrees well with the numerical solutions of compressible boundary layer and the Navier-Stokes equations. An exhaustive search using the analytical model to compute the microchip temperature distribution is performed for thermal optimization of microchip placement on a printed wiring board. It is found the high-power chips should be mounted near the leading edge of the board when there are a small number of high-power chips in the group. When the majority of the microchips are of high power consumption rates, there is no general rule for the optimal placement of the chips. In this case it is recommended that some of the high-power chips be mounted near the trailing edge to allow the air near the chip surfaces to cool down when passing over low-power chips or the adiabatic substrate.